RG82855GMESL72L Datasheet, PDF (34/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Signal Descriptions
R
3.3
AGP Interface Signals
Note: AGP interface is only supported on the Intel 855GME GMCH. Unless otherwise specified, the
voltage level for all signals in this interface is 1.5 volts.
3.3.1 AGP Addressing Signals
Table 5. AGP Addressing Signal Descriptions
Signal Name
GPIPE#
Type
I
AGP
Description
Pipelined Read: This signal is asserted by the AGP master to indicate a full width
address is to be enqueued on by the target using the AD bus. One address is placed in
the AGP request queue on each rising clock edge while PIPE# is asserted. When
PIPE# is deasserted no new requests are queued across the AD bus.
During SBA Operation: This signal is not used if SBA (Side Band Addressing) is
selected.
During FRAME# Operation: This signal is not used during AGP FRAME# operation.
PIPE# is a sustained tri-state signal from masters (graphics controller), and is an input
to the GMCH.
GSBA[7:0]
I
AGP
Side-band Address: These signals are used by the AGP master (graphics controller)
to pass address and command to the GMCH. The SBA bus and AD bus operate
independently. That is, transactions can proceed on the SBA bus and the AD bus
simultaneously.
During PIPE# Operation: These signals are not used during PIPE# operation.
During FRAME# Operation: These signals are not used during AGP FRAME#
operation.
NOTE: When sideband addressing is disabled, these signals are isolated (no
external/internal pull-ups are required).
Section 5 contains two mechanisms to queue requests by the AGP master. Note that the master
can only use one mechanism. The master may not switch methods without a full reset of the
system. When PIPE# is used to queue addresses the master is not allowed to queue addresses
using the SBA bus. For example, during configuration time, if the master indicates that it can use
either mechanism, the configuration software will indicate which mechanism the master will use.
Once this choice has been made, the master will continue to use the mechanism selected until the
master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic
mechanism, but rather a static decision when the device is first being configured after reset.
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Datasheet