RG82855GMESL72L Datasheet, PDF (165/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Power and Thermal Management
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7 Power and Thermal Management
7.1
The Intel 855GM/855GME GMCH chipset platform is intended to be compliant with the
following specifications and technologies:
• APM Rev 1.2
• PCI Power Management Rev 1.0
• PC’99, Rev 1.0, PC’99A, and PC’01, Rev 1.0
• ACPI 1.0b and 2.0 support
• ACPI S0, S1-M, S3, S4, S5, C0, C1, C2, C3 states
• Internal Graphics Adapter D0, D1, D3 (Hot/Cold)
• On Die Thermal sensor, enabling core and system memory Write Thermal throttling for
prevention of catastrophic thermal conditions
• External Thermal sensor input pin
• Enabling SO-DIMM Thermal throttling
• The GMCH also reduces I/O power dynamically, by disabling sense amps on input buffers,
as well as tristating output buffers when possible
• Dynamic Clock Power Down reduces power in all modes of operation
• System memory Self-Refresh in C3 state (Intel 855GME GMCH)
• Enhanced Intel SpeedStep technology (using Intel Pentium M processor)
• Flat Panel Power Sequencing
• Intel 855GM/GME GMCH reduces I/O power dynamically by disabling sense amps on the
input buffers, as well as tri-stating the output buffers when possible
General Description of Supported CPU States
C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK is
deasserted, and the processor core is active. The processor can service snoops and maintain cache
coherency in this state.
C1 (Auto Halt): The first level of power reduction occurs when the processor executes an Auto-
Halt instruction. This stops the execution of the instruction stream and reduces the processor’s
power consumption. The processor can service snoops and maintain cache coherency in this state.
C2 (Stop Grant): To enter this low power state, STPCLK is asserted. The processor can still
service snoops and maintain cache coherency in this state.
C3 (Sleep or Deep Sleep): In these states the processor clock is stopped. The GMCH assumes
that no Hub interface cycles (except special cycles) will occur while the GMCH is in this state.
The processor cannot snoop its caches to maintain coherency while in the C3 state. The GMCH
Datasheet
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