RG82855GMESL72L Datasheet, PDF (13/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

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Intel^® 855GM Chipset GMCH Features
ƒ ^{Processor/Host Bus Support}
ƒ ^{Video Stream Decoder}
⎯ Intel® Pentium® M processor and Intel®
⎯ Improved hardware motion compensation
Celeron® M processor
for MPEG2
⎯ 2X address, 4X data
⎯ All format decoder (18 ATSC formats)
⎯ Supports 400 MHz Front Side Bus (FSB)
supported
⎯ Supports Host bus dynamic bus inversion
⎯ Dynamic Bob and Weave support for video
(DBI)
streams
⎯ Supports 64-bit host data bus and 32-bit
⎯ Software DVD at 60 Fields/second and 30
addressing
frames/second full screen
⎯ 8-deep in-order queue
⎯ Support for standard definition DVD (i.e.
⎯ AGTL+ bus driver technology with
NTSC pixel resolution of 720x480, etc.)
integrated AGTL+ termination resistors and
quality encoding at low CPU utilization
low voltage operation (Vtt = 1.05 V)
ƒ ^{Video Overlay}
⎯ Supports Enhanced Intel SpeedStep^®
⎯ Single high quality scalable overlay and
technology (Intel Pentium M processor
second Sprite to support second overlay
⎯ Support for DPWR# signal to Intel Pentium ⎯ Multiple overlay functionality provided via
M processor and Intel Celeron M processor
arithmetic stretch BLT(Block Transfer)
for FSB power management
⎯ 5-tap horizontal, 3-tap vertical filtered
ƒ ^{Memory System}
scaling
⎯ Directly supports one DDR SDRAM
⎯ Multiple overlay formats
channel, 64-bits wide (72-bits with ECC)
⎯ Direct YUV from overlay to TV-out
⎯ Supports 200/266 MHz DDR SDRAM
⎯ Independent gamma correction
devices with max of two, double-sided SO- ⎯ Independent brightness / contrast/ saturation
DIMMs (four rows populated) with
⎯ Independent tint/hue support
unbuffered PC1600/PC2100 DDR SDRAM. _{⎯ Destination colorkeying}
⎯ Supports 128-Mbit, 256-Mbit, and 512-Mbit _{⎯ Source chromakeying}
technologies providing maximum capacity _{ƒ Multiple hardware color cursor support (32-bit}
of 1 GB with x16 devices and up to 2-GB
with alpha and legacy 2-bpp mode)
with high density 512-Mbit technology
⎯ All supported devices have four banks
ƒ ^{Accompanying I2C and DDC channels provided}
through multiplexed interface
⎯ Supports up to 16 simultaneous open pages _{ƒ Display}
⎯ Supports page sizes of 2-kB, 4-kB, 8-kB,
⎯ Analog display support
and 16-kB. Page size is individually
selected for every row
⎯ UMA support only
ƒ ^{System Interrupts}
⎯ Supports Intel 8259 and front side bus
interrupt delivery mechanism
⎯ Supports interrupts signaled as upstream
memory writes from PCI and Hub interface
⎯ MSI sent to the CPU through the system bus
⎯ IOxAPIC in ICH4-M provides redirection
for upstream interrupts to the system bus
• 350 MHz integrated 24-bit RAMDAC
that can drive a standard progressive
scan analog monitor with pixel
resolution up to 1600x1200 at 85 Hz
and up to 2048x1536 at 75 Hz
⎯ Dual independent pipe support
• Concurrent: different images and native
display timings on each display device
• Simultaneous: same images and native
display timings on each display device
Datasheet
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