RG82855GMESL72L Datasheet, PDF (157/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
R
Table 38. Panel Power Sequencing Timing Parameters
Name
T1+T2
T5
TX
T3
T4
Panel Power Sequence Timing Parameters
Spec Name
From
To
Vdd On to LVDS Active
Panel Vdd must be on for a minimum time before the LVDS data
stream is enabled.
Backlight
LVDS data must be enabled for a minimum time before the backlight
is turned on.
Backlight State
Backlight must be disabled for a minimum time before the LVDS
data stream is stopped.
LVDS State
Data must be off for a minimum time before the panel VDD is turned
off.
Power cycle Delay
When panel VDD is turned from On to Off, a minimum wait must be
satisfied before the panel VDD is enabled again.
.1 Vdd
LVDS Active
Backlight Off
LVDS Off
Power Off
LVDS Active
Backlight on
LVDS off
Start power
off
Power On
Sequence
Start
6.5.2.8
6.5.2.9
Back Light Inverter Control
The GMCH offers integrated PWM for TFT panel Backlight Inverter control. Other methods of
control are specified below:
• SMBus-based Backlight Brightness Control
• GMBus-based Backlight Brightness Control
• PWM – based Backlight Brightness Control
• DBL(Display Brightness Link) –to- VDL (Video Data Link) Power Sequencing.
Digital Video Output Port
The GMCH has the capability to support additional digital display devices (e.g. TMDS
transmitter, LVDS transmitter or TV-out encoder) through its digital video output port. DVOB
and C can each deliver a 165 MHz dot clock on each of their 12-bit interfaces, or 330 MHz dot
clock on a combined 24-bit interface.
The digital display port consists of a digital data bus, VSYNC, HSYNC, and BLANK# signals.
The data bus can operate only in a 12-bit mode. Embedded sync information or HSYNC and
VSYNC signals can optionally provide the basic timing information to the external device and the
BLANK# signal indicates which clock cycles contain valid data. The BLANK# signal can be
optionally selected to include the border area of the timing. The VSYNC and HSYNC signals can
be disabled when embedded sync information is to be used or to support DPMS. Optionally a
STALL signal can cause the next line of data to not be sent until the STALL signal is removed.
Datasheet
157