RG82855GMESL72L Datasheet, PDF (160/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Functional Description
R
The 4X data rate transfer provides 1.06 GB/s transfer rates. The control signal protocol for the 4X
data transfer protocol is identical to 1X/2X protocol. In 4X mode 16 bytes of data are transferred
on every 66 MHz clock edge. The minimum throttleable block size remains four, 66 MHz clocks,
which means 64 bytes of data are transferred per block. Three additional signal pins are required
to implement the 4X data transfer protocol. These signal pins are complementary data transfer
strobes for the AD bus (2) and the SBA bus (1).
6.5.5.1 Fast Writes
The GMCH supports 2X and 4X Fast Writes from the GMCH to the graphics controller on AGP.
Fast Write operation is compliant with the AGP 2.0 specification.
The GMCH will not generate Fast Back to Back (FB2B) cycles in 1X mode, but will generate
FB2B cycles in 2X and 4X Fast Write modes.
To use the Fast Write protocol, the Fast Write Enable configuration bit, AGPCMD[FWEN] (bit 4
of the AGP Command Register), must be set to 1.
Memory writes originating from the host or from the hub interface use the Fast Write protocol
when it is both capability enabled and enabled. The data rate used to perform the Fast Writes is
dependent on the bits set in the AGP Command Register bits 2:0 (DATA_RATE). If bit 2 of the
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 4X strobing. If bit 1 of
AGPCMD[DATA_RATE] field is 1, the data transfers occur using 2X strobing. If bit 0 of
AGPCMD[DATA_RATE] field is 1, Fast Writes are disabled and data transfers occur using
standard PCI protocol. Note that only one of the three DATA_RATE bits may be set by
initialization software. This is summarized in the following table.
Table 40. Fast Write Initialization
FWEN
0
1
1
1
DATA_RATE
[2]
X
0
0
1
DATA_RATE
[1]
x
0
1
0
DATA_RATE
[0]
x
1
0
0
GMCH =>AGP Master Write
Protocol
1X
1X
2X Strobing
4X Strobing
6.5.5.2
AGP FRAME# Transactions on AGP
The GMCH accepts and generates AGP FRAME# transactions on the AGP bus. The GMCH
guarantees that AGP FRAME# accesses to DRAM are kept coherent with the processor caches by
generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not supported.
GMCH Initiator and Target Operations
Table 41 summarizes GMCH target operation for AGP FRAME# initiators. The cycles can be
either destined to main memory or the hub interface.
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Datasheet