RG82855GMESL72L Datasheet, PDF (106/213 Pages) Intel Corporation – Intel® 855GM/855GME Chipset Graphics and Memory Controller Hub (GMCH)

Register Description
R
4.10.1
VID – Vendor Identification Register
The VID Register contains the vendor identification number. This 16-bit register combined with
the Device Identification register uniquely identifies any PCI device. Writes to this register have
no effect.
Bit
15:0
Description
Vendor Identification (VID): This register field contains the PCI standard identification for 8086h.
4.10.2
DID – Device Identification Register
Address Offset:
Default Value:
Access:
Size:
02-03h
3585h
Read Only
16 bits
This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI
device. Writes to this register have no effect.
Bit
15:0
Description
Device Identification Number (DID): This is a 16-bit value assigned to the Intel 855GM/GME GMCH
Host-HI Bridge Function #3 (3585h).
4.10.3
PCICMD – PCI Command Register
Address Offset:
Default Value:
Access:
Size:
04-05h
0006h
Read Only, Read/Write
16 bits
Since Intel 855GM/GME GMCH Device #0 does not physically reside on PCI_A many of the bits
are not implemented.
Bit
15:10
9
8
7
6
5
Description
Reserved
Fast Back-to-Back Enable (FB2B): This bit controls whether or not the master can do fast back-to-
back Write. Since Device #0 is strictly a target, this bit is not implemented and is hardwired to 0. Writes
to this bit position have no effect.
SERR Enable (SERRE): SERR# is not implemented by Function #1 of Device #0 of the GMCH and this
bit is hardwired to 0. Writes to this bit position have no effect.
Address/Data Stepping Enable (ADSTEP): Address/data stepping is not implemented in the GMCH,
and this bit is hardwired to 0. Writes to this bit position have no effect.
Parity Error Enable (PERRE): PERR# is not implemented by GMCH and this bit is hardwired to 0.
Writes to this bit position have no effect.
VGA Palette Snoop Enable (VGASNOOP): The GMCH does not implement this bit and it is hardwired
to a 0. Writes to this bit position have no effect.
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Datasheet