MC9S08AW16CFUE Datasheet, PDF (98/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 6 Parallel Input/Output
6.7.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS)
In addition to the I/O control, port D pins are controlled by the registers listed below.
R
W
Reset
7
PTDPE7
0
6
PTDPE6
5
PTDPE5
4
PTDPE4
3
PTDPE3
2
PTDPE2
0
0
0
0
0
Figure 6-26. Internal Pullup Enable for Port D (PTDPE)
1
PTDPE1
0
0
PTDPE0
0
Table 6-19. PTDPE Register Field Descriptions
Field
Description
7:0
PTDPE[7:0]
Internal Pullup Enable for Port D Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port D bit n.
1 Internal pullup device enabled for port D bit n.
R
W
Reset
7
PTDSE7
0
6
PTDSE6
5
PTDSE5
4
PTDSE4
3
PTDSE3
2
PTDSE2
1
PTDSE1
0
0
0
0
0
0
Figure 6-27. Output Slew Rate Control Enable for Port D (PTDSE)
0
PTDSE0
0
Table 6-20. PTDSE Register Field Descriptions
Field
Description
7:0
PTDSE[7:0]
Output Slew Rate Control Enable for Port D Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
MC9S08AW60 Data Sheet, Rev 2
98
Freescale Semiconductor