MC9S08AW16CFUE Datasheet, PDF (95/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 6 Parallel Input/Output
6.7.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS)
In addition to the I/O control, port C pins are controlled by the registers listed below.
7
R
W
Reset
0
6
PTCPE6
5
PTCPE5
4
PTCPE4
3
PTCPE3
2
PTCPE2
0
0
0
0
0
Figure 6-21. Internal Pullup Enable for Port C (PTCPE)
1
PTCPE1
0
0
PTCPE0
0
Table 6-14. PTCPE Register Field Descriptions
Field
Description
6:0
PTCPE[6:0]
Internal Pullup Enable for Port C Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTC pin. For port C pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port C bit n.
1 Internal pullup device enabled for port C bit n.
7
R
W
6
PTCSE6
5
PTCSE5
4
PTCSE4
3
PTCSE3
2
PTCSE2
1
PTCSE1
0
PTCSE0
Reset
0
0
0
0
0
0
0
0
Figure 6-22. Output Slew Rate Control Enable for Port C (PTCSE)
Table 6-15. PTCSE Register Field Descriptions
Field
Description
6:0
PTCSE[6:0]
Output Slew Rate Control Enable for Port C Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTC pin. For port C pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port C bit n.
1 Output slew rate control enabled for port C bit n.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
95