MC9S08AW16CFUE Datasheet, PDF (224/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 13 Inter-Integrated Circuit (S08IICV1)
13.3.5 IIC Data I/O Register (IIC1D)
7
6
5
4
3
2
1
0
R
DATA
W
Reset
0
0
0
0
0
0
0
0
Figure 13-7. IIC Data I/O Register (IIC1D)
Table 13-6. IIC1D Register Field Descriptions
Field
7:0
DATA
Description
Data — In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
NOTE
When transmitting out of master receive mode, the IIC mode should be
switched before reading the IIC1D register to prevent an inadvertent
initiation of a master receive data transfer.
In slave mode, the same functions are available after an address match has occurred.
Note that the TX bit in IIC1C must correctly reflect the desired direction of transfer in master and slave
modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master
receive is desired, then reading the IIC1D will not initiate the receive.
Reading the IIC1D will return the last byte received while the IIC is configured in either master receive or
slave receive modes. The IIC1D does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IIC1D correctly by reading it back.
In master transmit mode, the first byte of data written to IIC1D following assertion of MST is used for the
address transfer and should comprise of the calling address (in bit 7–bit 1) concatenated with the required
R/W bit (in position bit 0).
MC9S08AW60 Data Sheet, Rev 2
224
Freescale Semiconductor