MC9S08AW16CFUE Datasheet, PDF (257/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 14 Analog-to-Digital Converter (S08ADC10V1)
14.7.2 Sources of Error
Several sources of error exist for A/D conversions. These are discussed in the following sections.
14.7.2.1 Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the
maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling
to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @
8 MHz maximum ADCK frequency) provided the resistance of the external analog source (R_AS) is kept
below 5 kΩ.
Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the
sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
14.7.2.2 Pin Leakage Error
Leakage on
If this error
the I/O pins can cause conversion error if the external
cannot be tolerated by the application, keep R_AS lower
analog source
than V_DDAD /
r(e2s_Ni*stIa_Ln_Ec_Ae_K()Rf_AorS)leissshtihgahn.
1/4LSB leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode).
14.7.2.3 Noise-Induced Errors
System noise which occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
• There is a 0.1 μF low-ESR capacitor from V_REFH to V_REFL.
• There is a 0.1 μF low-ESR capacitor from V_DDAD to V_SSAD.
• If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from
V_DDAD to V_SSAD.
• V_SSAD (and V_REFL, if connected) is connected to V_SS at a quiet point in the ground plane.
• Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to the ADC1SC1 with a
WAIT instruction or STOP instruction.
— For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces V_DD
noise but increases effective conversion time due to stop recovery.
• There is no I/O switching, input or output, on the MCU during the conversion.
There are some situations where external system activity causes radiated or conducted noise emissions or
excessive V_DD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise
on the accuracy:
• Place a 0.01 μF capacitor (C_AS) on the selected input channel to V_REFL or V_SSAD (this will
improve noise issues but will affect sample rate based on the external analog source resistance).
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
257