MC9S08AW16CFUE Datasheet, PDF (146/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 8 Internal Clock Generator (S08ICGV4)
8.4.10 Clock Mode Requirements
A clock mode is requested by writing to CLKS1:CLKS0 and the actual clock mode is indicated by
CLKST1:CLKST0. Provided minimum conditions are met, the status shown in CLKST1:CLKST0 should
be the same as the requested mode in CLKS1:CLKS0. Table 8-9 shows the relationship between CLKS,
CLKST, and ICGOUT. It also shows the conditions for CLKS = CLKST or the reason CLKS ≠ CLKST.
NOTE
If a crystal will be used before the next reset, then be sure to set REFS = 1
and CLKS = 1x on the first write to the ICGC1 register. Failure to do so will
result in “locking” REFS = 0 which will prevent the oscillator amplifier
from being enabled until the next reset occurs.
Table 8-9. ICG State Table
Actual
Mode
(CLKST)
Desired
Mode
(CLKS)
Range
Reference
Frequency
(f_REFERENCE)
Comparison
Cycle Time
ICGOUT
Conditions¹ for
CLKS = CLKST
Reason
CLKS1 ≠
CLKST
Off
Off
(XX)
X
0
—
0
(XX)
FBE
(10)
X
0
—
0
—
—
—
ERCS = 0
SCM
(00)
Not switching
X
f_ICGIRCLK/7²
8/f_ICGIRCLK
ICGDCLK/R
from FBE to
SCM
—
FEI
SCM
(01)
0
f_ICGIRCLK/7⁽¹⁾
8/f_ICGIRCLK
ICGDCLK/R
—
DCOS = 0
(00)
FBE
(10)
X
f_ICGIRCLK/7⁽¹⁾
8/f_ICGIRCLK
ICGDCLK/R
—
ERCS = 0
FEE
(11)
X
f_ICGIRCLK/7⁽¹⁾
8/f_ICGIRCLK
ICGDCLK/R
—
DCOS = 0 or
ERCS = 0
FEI
FEI
(01)
0
f_ICGIRCLK/7
8/f_ICGIRCLK
ICGDCLK/R
DCOS = 1
—
(01)
FEE
(11)
X
f_ICGIRCLK/7
8/f_ICGIRCLK
ICGDCLK/R
—
ERCS = 0
FBE
FBE
(10)
X
0
(10)
FEE
(11)
X
0
—
ICGERCLK/R
ERCS = 1
—
—
ICGERCLK/R
—
LOCS = 1 &
ERCS = 1
FEE
FEE
0
f_ICGERCLK
2/f_ICGERCLK
ICGDCLK/R³
ERCS = 1 and
DCOS = 1
—
(11)
(11)
1
f_ICGERCLK
128/f_{ICGERCLK ICGDCLK/R}⁽²⁾
ERCS = 1 and
DCOS = 1
—
1 _{CLKST will not update immediately after a write to CLKS. Several bus cycles are required before CLKST updates to the new}
value.
2 _{The reference frequency has no effect on ICGOUT in SCM, but the reference frequency is still used in making the comparisons}
that determine the DCOS bit
3 _{After initial LOCK; will be ICGDCLK/2R during initial locking process and while FLL is re-locking after the MFD bits are changed.}
MC9S08AW60 Data Sheet, Rev 2
146
Freescale Semiconductor