MC9S08AW16CFUE Datasheet, PDF (85/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

6.3.6 Port F
Chapter 6 Parallel Input/Output
Port F
Bit 7
MCU Pin: PTF7
6
5
4
3
2
1
Bit 0
PTF6
PTF5/
PTF4/
PTF3/
PTF2/
PTF1/
PTF0/
TPM2CH1 TPM2CH0 TPM1CH5 TPM1CH4 TPM1CH3 TPM1CH2
Figure 6-6. Port F Pin Names
Port F pins are general-purpose I/O pins. Parallel I/O function is controlled by the port F data (PTFD) and
data direction (PTFDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTFPE), slew rate control (PTFSE), and drive strength select (PTFDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port F general-purpose I/O is shared with TPM1 and TPM2 timer channels. When any of these shared
functions is enabled, the direction, input or output, is controlled by the shared function and not by the data
direction register of the parallel I/O port. Also, for pins which are configured as outputs by the shared
function, the output data is controlled by the shared function and not by the port data register.
Refer to Chapter 10, “Timer/PWM (S08TPMV2)” for more information about using port F pins as TPM
channel pins.
6.3.7 Port G
Port G
Bit 7
MCU Pin:
6
5
4
3
PTG6/ PTG5/ PTG4/ PTG3/
EXTAL XTAL KBI1P4 KBI1P3
Figure 6-7. Port G Pin Names
2
PTG2/
KBI1P2
1
PTG1/
KBI1P1
Bit 0
PTG0/
KBI1P0
Port G pins are general-purpose I/O pins. Parallel I/O function is controlled by the port G data (PTGD) and
data direction (PTGDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTGPE), slew rate control (PTGSE), and drive strength select (PTGDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port G general-purpose I/O is shared with KBI, XTAL, and EXTAL. When a pin is enabled as a KBI input,
the pin functions as an input regardless of the state of the associated PTG data direction register bit. When
the external oscillator is enabled, PTG5 and PTG6 function as oscillator pins. In this case the associated
parallel I/O and pin control registers have no control of the pins.
Refer to Chapter 8, “Internal Clock Generator (S08ICGV4)” for more information about using port G pins
as XTAL and EXTAL pins.
Refer to Chapter 9, “Keyboard Interrupt (S08KBIV1)” for more information about using port G pins as
keyboard inputs.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
85