MC9S08AW16CFUE Datasheet, PDF (240/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 14 Analog-to-Digital Converter (S08ADC10V1)
7
6
5
4
R COCO
W
AIEN
ADCO
3
2
1
0
ADCH
Reset:
0
0
0
1
1
1
1
1
= Unimplemented or Reserved
Figure 14-3. Status and Control Register (ADC1SC1)
Table 14-3. ADC1SC1 Register Field Descriptions
Field
7
COCO
6
AIEN
5
ADCO
4:0
ADCH
Description
Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is
completed when the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE =
1) the COCO flag is set upon completion of a conversion only if the compare result is true. This bit is cleared
whenever ADC1SC1 is written or whenever ADC1RL is read.
0 Conversion not completed
1 Conversion completed
Interrupt Enable — AIEN is used to enable conversion complete interrupts. When COCO becomes set while
AIEN is high, an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
Continuous Conversion Enable — ADCO is used to enable continuous conversions.
0 One conversion following a write to the ADC1SC1 when software triggered operation is selected, or one
conversion following assertion of ADHWT when hardware triggered operation is selected.
1 Continuous conversions initiated following a write to ADC1SC1 when software triggered operation is selected.
Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.
Input Channel Select — The ADCH bits form a 5-bit field which is used to select one of the input channels. The
input channels are detailed in Figure 14-4.
The successive approximation converter subsystem is turned off when the channel select bits are all set to 1.
This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources.
Terminating continuous conversions this way will prevent an additional, single conversion from being performed.
It is not necessary to set the channel select bits to all 1s to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
ADCH
00000
00001
00010
00011
00100
00101
00110
00111
Figure 14-4. Input Channel Select
Input Select
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ADCH
10000
10001
10010
10011
10100
10101
10110
10111
Input Select
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
MC9S08AW60 Data Sheet, Rev 2
240
Freescale Semiconductor