MC9S08AW16CFUE Datasheet, PDF (135/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 8 Internal Clock Generator (S08ICGV4)
8.3 Register Definition
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all ICG registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
8.3.1 ICG Control Register 1 (ICGC1)
7
6
5
4
3
2
1
0
R
HGO¹
W
RANGE
REFS
CLKS
0
OSCSTEN
LOCD
Reset
0
1
0
0
0
1
0
0
= Unimplemented or Reserved
Figure 8-6. ICG Control Register 1 (ICGC1)
1 _{This bit can be written only once after reset. Additional writes are ignored.}
Table 8-1. ICGC1 Register Field Descriptions
Field
7
HGO
6
RANGE
5
REFS
4:3
CLKS
Description
High Gain Oscillator Select — The HGO bit is used to select between low power operation and high gain
operation for improved noise immunity. This bit is write-once after reset.
0 Oscillator configured for low power operation.
1 Oscillator configured for high gain operation.
Frequency Range Select — The RANGE bit controls the oscillator, reference divider, and FLL loop prescaler
multiplication factor (P). It selects one of two reference frequency ranges for the ICG. The RANGE bit is
write-once after a reset. The RANGE bit only has an effect in FLL engaged external and FLL bypassed external
modes.
0 Oscillator configured for low frequency range. FLL loop prescale factor P is 64.
1 Oscillator configured for high frequency range. FLL loop prescale factor P is 1.
External Reference Select — The REFS bit controls the external reference clock source for ICGERCLK. The
REFS bit is write-once after a reset.
0 External clock requested.
1 Oscillator using crystal or resonator requested.
Clock Mode Select — The CLKS bits control the clock mode as described below. If FLL bypassed external is
requested, it will not be selected until ERCS = 1. If the ICG enters off mode, the CLKS bits will remain
unchanged. Writes to the CLKS bits will not take effect if a previous write is not complete.
00 Self-clocked
01 FLL engaged, internal reference
10 FLL bypassed, external reference
11 FLL engaged, external reference
The CLKS bits are writable at any time, unless the first write after a reset was CLKS = 0X, the CLKS bits cannot
be written to 1X until after the next reset (because the EXTAL pin was not reserved).
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
135