MC9S08AW16CFUE Datasheet, PDF (174/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 10 Timer/Pulse-Width Modulator (S08TPMV2)
CPWMS
X
0
1
MSnB:MSnA
XX
00
01
1X
XX
Table 10-5. Mode, Edge, and Level Selection
ELSnB:ELSnA
00
01
10
11
00
01
10
11
10
X1
10
X1
Mode
Configuration
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
Input capture Capture on rising edge only
Output
compare
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Edge-aligned
PWM
Center-aligned
PWM
High-true pulses (clear output on compare)
Low-true pulses (set output on compare)
High-true pulses (clear output on compare-up)
Low-true pulses (set output on compare-up)
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
10.4.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
7
6
5
4
3
2
R
Bit 15
14
13
12
11
10
W
1
0
9
Bit 8
Reset
0
0
0
0
0
0
0
0
Figure 10-9. Timer x Channel Value Register High (TPMxCnVH)
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 10-10. Timer Channel Value Register Low (TPMxCnVL)
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other byte is read. This latching mechanism also resets
(becomes unlatched) when the TPMxCnSC register is written.
MC9S08AW60 Data Sheet, Rev 2
174
Freescale Semiconductor