MC9S08AW16CFUE Datasheet, PDF (142/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 8 Internal Clock Generator (S08ICGV4)
entering off mode. If CLKS bits are set to 01 or 11 coming out of the Off state, the ICG enters this mode
until ICGDCLK is stable as determined by the DCOS bit. After ICGDCLK is considered stable, the ICG
automatically closes the loop by switching to FLL engaged (internal or external) as selected by the CLKS
bits.
CLKST
CLKS
RFD
REFERENCE
DIVIDER (/7)
RANGE
MFD
ICGIRCLK
FLT
CLOCK
SELECT
CIRCUIT
ICGDCLK
REDUCED
FREQUENCY
ICGOUT
DIVIDER (R)
SUBTRACTOR
DIGITAL
LOOP
FILTER
CLKST
DIGITALLY ^1x
CONTROLLED
OSCILLATOR
2x
FLL ANALOG
OVERFLOW
COUNTER ENABLE
RANGE
LOCK AND
LOSS OF CLOCK
DETECTOR
PULSE
COUNTER
ICG2DCLK
RESET AND
INTERRUPT
CONTROL
FREQUENCY-
LOCKED
LOOP (FLL)
IRQ
RESET
DCOS LOCK LOLS LOCS ERCS LOCD
ICGIF LOLRE LOCRE
Figure 8-13. Detailed Frequency-Locked Loop Block Diagram
8.4.3 FLL Engaged, Internal Clock (FEI) Mode
FLL engaged internal (FEI) is entered when any of the following conditions occur:
• CLKS bits are written to 01
• The DCO clock stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 01
In FLL engaged internal mode, the reference clock is derived from the internal reference clock
ICGIRCLK, and the FLL loop will attempt to lock the ICGDCLK frequency to the desired value, as
selected by the MFD bits.
MC9S08AW60 Data Sheet, Rev 2
142
Freescale Semiconductor