MC9S08AW16CFUE Datasheet, PDF (300/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Appendix A Electrical Characteristics and Timing Specifications
A.10 AC Characteristics
This section describes ac timing characteristics for each peripheral system. For detailed information about
how clocks for the bus are generated, see Chapter 8, “Internal Clock Generator (S08ICGV4).”
A.10.1 Control Timing
Table A-13. Control Timing
Num C
Parameter
Symbol
Min
Typ¹
Max
Unit
1
Bus frequency (t_cyc = 1/f_Bus)
f_Bus
dc
—
20
MHz
2
P Real-time interrupt internal oscillator period
t_RTI
700
1300
μs
3
External reset pulse width²
(t_cyc = 1/f_{Self_reset})
t_extrst
1.5 x
t_{Self_reset}
—
ns
4
Reset low drive³
t_rstdrv
34 x t_cyc
—
ns
5
Active background debug mode latch setup time
t_MSSU
25
—
ns
6
Active background debug mode latch hold time
t_MSH
25
—
ns
IRQ pulse width
7
Asynchronous path²
Synchronous path⁴
t_ILIH, t_IHIL
100
—
—
ns
1.5 x t_cyc
8
KBIPx pulse width
Asynchronous path²
Synchronous path³
t_ILIH, t_IHIL
100
—
—
ns
1.5 x t_cyc
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)⁵
Slew rate control disabled (PTxSE = 0)
t_Rise, t_Fall
—
40
—
ns
Slew rate control enabled (PTxSE = 1)
9
T
Port rise and fall time —
—
75
—
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
t_Rise, t_Fall
—
11
—
ns
Slew rate control enabled (PTxSE = 1)
—
35
—
1 _{Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to}
override reset requests from internal sources.
3 _{When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on}
the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests.
4 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.}
MC9S08AW60 Data Sheet, Rev 2
300
Freescale Semiconductor