MC9S08AW16CFUE Datasheet, PDF (69/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 5 Resets, Interrupts, and System Configuration
NOTE
The voltage measured on the pulled up IRQ pin may be as low as
V_DD – 0.7 V. The internal gates connected to this pin are pulled all the way
to V_DD. All other pins with enabled pullup resistors will have an unloaded
measurement of V_DD.
5.5.2.2 Edge and Level Sensitivity
The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In this
edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin
changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared)
as long as the IRQ pin remains at the asserted level.
5.5.3 Interrupt Vectors, Sources, and Local Masks
Table 5-1 provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction, stack the PCL, PCH, X, A, and CCR CPU
registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
69