MC9S08AW16CFUE Datasheet, PDF (104/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 6 Parallel Input/Output
6.7.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS)
In addition to the I/O control, port F pins are controlled by the registers listed below.
R
W
Reset
7
PTFPE7
0
6
PTFPE6
5
PTFPE5
4
PTFPE4
3
PTFPE3
2
PTFPE2
0
0
0
0
0
Figure 6-36. Internal Pullup Enable for Port F (PTFPE)
1
PTFPE1
0
0
PTFPE0
0
Table 6-29. PTFPE Register Field Descriptions
Field
Description
7:0
PTFPE[7:0]
Internal Pullup Enable for Port F Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTF pin. For port F pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port F bit n.
1 Internal pullup device enabled for port F bit n.
R
W
Reset
7
PTFSE7
0
6
PTFSE6
5
PTFSE5
4
PTFSE4
3
PTFSE3
2
PTFSE2
1
PTFSE1
0
0
0
0
0
0
Figure 6-37. Output Slew Rate Control Enable for Port F (PTFSE)
0
PTFSE0
0
Table 6-30. PTFSE Register Field Descriptions
Field
Description
7:0
PTFSE[7:0]
Output Slew Rate Control Enable for Port F Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTF pin. For port F pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port F bit n.
1 Output slew rate control enabled for port F bit n.
MC9S08AW60 Data Sheet, Rev 2
104
Freescale Semiconductor