MC9S08AW16CFUE Datasheet, PDF (261/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 15
Development Support
15.1 Introduction
Development support systems in the HCS08 include the background debug controller (BDC) and the
on-chip debug module (DBG). The BDC provides a single-wire debug interface to the target MCU that
provides a convenient interface for programming the on-chip FLASH and other nonvolatile memories. The
BDC is also the primary debug interface for development and allows non-intrusive access to memory data
and traditional debug features such as CPU register modify, breakpoints, and single instruction trace
commands.
In the HCS08 family, address and data bus signals are not available on external pins (not even in test
modes). Debug is done through commands fed into the target MCU via the single-wire background debug
interface. The debug module provides a means to selectively trigger and capture bus information so an
external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis
without having external access to the address and data signals.
The alternate BDC clock source for MC9S08AW60 Series is the ICGLCLK. See Chapter 8, “Internal
Clock Generator (S08ICGV4)” for more information about ICGCLK and how to select clock sources.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
261