MC9S08AW16CFUE Datasheet, PDF (100/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 6 Parallel Input/Output
6.7.9 Port E I/O Registers (PTED and PTEDD)
Port E parallel I/O function is controlled by the registers listed below.
R
W
Reset
7
PTED7
0
6
PTED6
5
PTED5
4
PTED4
3
PTED3
2
PTED2
0
0
0
0
0
Figure 6-29. Port E Data Register (PTED)
1
PTED1
0
0
PTED0
0
Table 6-22. PTED Register Field Descriptions
Field
Description
7:0
PTED[7:0]
Port E Data Register Bits — For port E pins that are inputs, reads return the logic level on the pin. For port E
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTED to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
R
W
Reset
7
PTEDD7
0
6
PTEDD6
5
PTEDD5
4
PTEDD4
3
PTEDD3
2
PTEDD2
0
0
0
0
0
Figure 6-30. Data Direction for Port E (PTEDD)
1
PTEDD1
0
0
PTEDD0
0
Table 6-23. PTEDD Register Field Descriptions
Field
Description
7:0
Data Direction for Port E Bits — These read/write bits control the direction of port E pins and what is read for
PTEDD[7:0] PTED reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port E bit n and PTED reads return the contents of PTEDn.
MC9S08AW60 Data Sheet, Rev 2
100
Freescale Semiconductor