MC9S08AW16CFUE Datasheet, PDF (11/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Section Number
Title
Page
5.9.8 System Power Management Status and Control 1 Register (SPMSC1) .........................79
5.9.9 System Power Management Status and Control 2 Register (SPMSC2) .........................80
Chapter 6
Parallel Input/Output
6.1 Introduction .....................................................................................................................................81
6.2 Features ...........................................................................................................................................81
6.3 Pin Descriptions ..............................................................................................................................82
6.3.1 Port A ..............................................................................................................................82
6.3.2 Port B ..............................................................................................................................82
6.3.3 Port C ..............................................................................................................................83
6.3.4 Port D ..............................................................................................................................83
6.3.5 Port E ..............................................................................................................................84
6.3.6 Port F ..............................................................................................................................85
6.3.7 Port G ..............................................................................................................................85
6.4 Parallel I/O Control .........................................................................................................................86
6.5 Pin Control ......................................................................................................................................87
6.5.1 Internal Pullup Enable ....................................................................................................87
6.5.2 Output Slew Rate Control Enable ..................................................................................87
6.5.3 Output Drive Strength Select ..........................................................................................87
6.6 Pin Behavior in Stop Modes ............................................................................................................88
6.7 Parallel I/O and Pin Control Registers ............................................................................................88
6.7.1 Port A I/O Registers (PTAD and PTADD) .....................................................................88
6.7.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS) ..............................................89
6.7.3 Port B I/O Registers (PTBD and PTBDD) .....................................................................91
6.7.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) ..............................................92
6.7.5 Port C I/O Registers (PTCD and PTCDD) .....................................................................94
6.7.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) ..............................................95
6.7.7 Port D I/O Registers (PTDD and PTDDD) ....................................................................97
6.7.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) .............................................98
6.7.9 Port E I/O Registers (PTED and PTEDD) ....................................................................100
6.7.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS) .............................................101
6.7.11 Port F I/O Registers (PTFD and PTFDD) ....................................................................103
6.7.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) ..............................................104
6.7.13 Port G I/O Registers (PTGD and PTGDD) ..................................................................106
6.7.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ...........................................107
Chapter 7
Central Processor Unit (S08CPUV2)
7.1 Introduction ...................................................................................................................................109
7.1.1 Features .........................................................................................................................109
7.2 Programmer’s Model and CPU Registers .....................................................................................110
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
11