MC9S08AW16CFUE Datasheet, PDF (243/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 14 Analog-to-Digital Converter (S08ADC10V1)
R
W
Reset:
7
ADR7
0
6
ADR6
5
ADR5
4
ADR4
3
ADR3
2
ADR2
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-7. Data Result Low Register (ADC1RL)
1
ADR1
0
0
ADR0
0
14.4.5 Compare Value High Register (ADC1CVH)
This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper
two bits of the result following a conversion in 10-bit mode when the compare function is enabled.In 8-bit
operation, ADC1CVH is not used during compare.
7
6
5
4
3
2
1
0
R
0
0
0
0
W
ADCV9 ADCV8
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-8. Compare Value High Register (ADC1CVH)
14.4.6 Compare Value Low Register (ADC1CVL)
This register holds the lower 8 bits of the 10-bit compare value, or all 8 bits of the 8-bit compare value.
Bits ADCV7:ADCV0 are compared to the lower 8 bits of the result following a conversion in either 10-bit
or 8-bit mode.
R
W
Reset:
7
ADCV7
0
6
ADCV6
5
ADCV5
4
ADCV4
3
ADCV3
2
ADCV2
0
0
0
0
0
Figure 14-9. Compare Value Low Register(ADC1CVL)
1
ADCV1
0
0
ADCV0
0
14.4.7 Configuration Register (ADC1CFG)
ADC1CFG is used to select the mode of operation, clock source, clock divide, and configure for low power
or long sample time.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
243