MC9S08AW16CFUE Datasheet, PDF (228/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 13 Inter-Integrated Circuit (S08IICV1)
SCL1
SCL2
SCL
DELAY
START COUNTING HIGH PERIOD
INTERNAL COUNTER RESET
Figure 13-9. IIC Clock Synchronization
13.4.1.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
13.4.1.9 Clock Stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
13.5 Resets
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
13.6 Interrupts
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in Table 13-7 occur provided the IICIE bit
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a one to it in the interrupt routine.
The user can determine the interrupt type by reading the status register.
Table 13-7. Interrupt Summary
Interrupt Source
Complete 1-byte transfer
Match of received calling address
Arbitration Lost
Status
TCF
IAAS
ARBL
Flag
IICIF
IICIF
IICIF
Local Enable
IICIE
IICIE
IICIE
MC9S08AW60 Data Sheet, Rev 2
228
Freescale Semiconductor