MC9S08AW16CFUE Datasheet, PDF (141/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 8 Internal Clock Generator (S08ICGV4)
8.4.1 Off Mode (Off)
Normally when the CPU enters stop mode, the ICG will cease all clock activity and is in the off state.
However there are two cases to consider when clock activity continues while the CPU is in stop mode,
8.4.1.1 BDM Active
When the BDM is enabled, the ICG continues activity as originally programmed. This allows access to
memory and control registers via the BDC controller.
8.4.1.2 OSCSTEN Bit Set
When the oscillator is enabled in stop mode (OSCSTEN = 1), the individual clock generators are enabled
but the clock feed to the rest of the MCU is turned off. This option is provided to avoid long oscillator
startup times if necessary, or to run the RTI from the oscillator during stop3.
8.4.1.3 Stop/Off Mode Recovery
Upon the CPU exiting stop mode due to an interrupt, the previously set control bits are valid and the system
clock feed resumes. If FEE is selected, the ICG will source the internal reference until the external clock
is stable. If FBE is selected, the ICG will wait for the external clock to stabilize before enabling ICGOUT.
Upon the CPU exiting stop mode due to a reset, the previously set ICG control bits are ignored and the
default reset values applied. Therefore the ICG will exit stop in SCM mode configured for an
approximately 8 MHz DCO output (4 MHz bus clock) with trim value maintained. If using a crystal, 4096
clocks are detected prior to engaging ICGERCLK. This is incorporated in crystal start-up time.
8.4.2 Self-Clocked Mode (SCM)
Self-clocked mode (SCM) is the default mode of operation and is entered when any of the following
conditions occur:
• After any reset.
• Exiting from off mode when CLKS does not equal 10. If CLKS = X1, the ICG enters this state
temporarily until the DCO is stable (DCOS = 1).
• CLKS bits are written from X1 to 00.
• CLKS = 1X and ICGERCLK is not detected (both ERCS = 0 and LOCS = 1).
In this state, the FLL loop is open. The DCO is on, and the output clock signal ICGOUT frequency is given
by f_ICGDCLK / R. The ICGDCLK frequency can be varied from 8 MHz to 40 MHz by writing a new value
into the filter registers (ICGFLTH and ICGFLTL). This is the only mode in which the filter registers can
be written.
If this mode is entered due to a reset, f_ICGDCLK will default to f_{Self_reset} which is nominally 8 MHz. If this
mode is entered from FLL engaged internal, f_ICGDCLK will maintain the previous frequency.If this mode
is entered from FLL engaged external (either by programming CLKS or due to a loss of external reference
clock), f_ICGDCLK will maintain the previous frequency, but ICGOUT will double if the FLL was unlocked.
If this mode is entered from off mode, f_ICGDCLK will be equal to the frequency of ICGDCLK before
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
141