MC9S08AW16CFUE Datasheet, PDF (144/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 8 Internal Clock Generator (S08ICGV4)
8.4.7.1 FLL Engaged External Unlocked
FEE unlocked is entered when FEE is entered and the count error (Δn) output from the subtractor is greater
than the maximum n_unlock or less than the minimum n_unlock, as required by the lock detector to detect the
unlock condition.
The ICG will remain in this state while the count error (Δn) is greater than the maximum n_lock or less than
the minimum n_lock, as required by the lock detector to detect the lock condition.
In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to
lock it according to their operational descriptions later in this section. Upon entering this state and until
the FLL becomes locked, the output clock signal ICGOUT frequency is given by f_ICGDCLK / (2×R) This
extra divide by two prevents frequency overshoots during the initial locking process from exceeding
chip-level maximum frequency specifications. After the FLL has locked, if an unexpected loss of lock
causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal
ICGOUT frequency is given by f_ICGDCLK / R.
8.4.7.2 FLL Engaged External Locked
FEE locked is entered from FEE unlocked when the count error (Δn) is less than n_lock (max) and greater
than n_lock (min) for a given number of samples, as required by the lock detector to detect the lock
condition. The output clock signal ICGOUT frequency is given by f_ICGDCLK/R. In FLL engaged external
locked, the filter value is updated only once every four comparison cycles. The update made is an average
of the error measurements taken in the four previous comparisons.
8.4.8 FLL Lock and Loss-of-Lock Detection
To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO
for one comparison cycle (see Table 8-9 for explanation of a comparison cycle) and passes this number to
the subtractor. The subtractor compares this value to the value in MFD and produces a count error, Δn. To
achieve locked status, Δn must be between n_lock (min) and n_lock (max). After the FLL has locked, Δn must
stay between n_unlock (min) and n_unlock (max) to remain locked. If Δn goes outside this range unexpectedly,
the LOLS status bit is set and remains set until cleared by software or until the MCU is reset. LOLS is
cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced reset
(LOLRE = 1), or by any MCU reset.
If the ICG enters the off state due to stop mode when ENBDM = OSCSTEN = 0, the FLL loses locked
status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock
condition. Though it would be unusual, if ENBDM is cleared to 0 while the MCU is in stop, the ICG enters
the off state. Because this is an unexpected stopping of clocks, LOLS will be set when the MCU wakes up
from stop.
Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the
TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the
LOLS will not be set.
MC9S08AW60 Data Sheet, Rev 2
144
Freescale Semiconductor