MC9S08AW16CFUE Datasheet, PDF (84/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 6 Parallel Input/Output
pullup enable (PTDPE), slew rate control (PTDSE), and drive strength select (PTDDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port D general-purpose I/O are shared with the ADC, KBI, and TPM1 and TPM2 external clock inputs.
When any of these shared functions is enabled, the direction, input or output, is controlled by the shared
function and not by the data direction register of the parallel I/O port. When a pin is shared with both the
ADC and a digital peripheral function, the ADC has higher priority. For example, in the case that both the
ADC and the KBI are configured to use PTD7 then the pin is controlled by the ADC module.
Refer to Chapter 10, “Timer/PWM (S08TPMV2)” for more information about using port D pins as TPM
external clock inputs.
Refer to Chapter 14, “Analog-to-Digital Converter (S08ADC10V1)” for more information about using
port D pins as analog inputs.
Refer to Chapter 9, “Keyboard Interrupt (S08KBIV1)” for more information about using port D pins as
keyboard inputs.
6.3.5 Port E
Port E
Bit 7
MCU Pin:
PTE7/
SPSCK1
6
5
4
3
2
PTE6/
MOSI1
PTE5/
MISO1
PTE4/ PTE3/ PTE2/
SS1 TPM1CH1 TPM1CH0
Figure 6-5. Port E Pin Names
1
PTE1/
RxD1
Bit 0
PTE0/
TxD1
Port E pins are general-purpose I/O pins. Parallel I/O function is controlled by the port E data (PTED) and
data direction (PTEDD) registers which are located in page zero register space. The pin control registers,
pullup enable (PTEPE), slew rate control (PTESE), and drive strength select (PTEDS) are located in the
high page registers. Refer to Section 6.4, “Parallel I/O Control” for more information about
general-purpose I/O control and Section 6.5, “Pin Control” for more information about pin control.
Port E general-purpose I/O is shared with SCI1, SPI, and TPM1 timer channels. When any of these shared
functions is enabled, the direction, input or output, is controlled by the shared function and not by the data
direction register of the parallel I/O port. Also, for pins which are configured as outputs by the shared
function, the output data is controlled by the shared function and not by the port data register.
Refer to Chapter 11, “Serial Communications Interface (S08SCIV2)” for more information about using
port E pins as SCI pins.
Refer to Chapter 12, “Serial Peripheral Interface (S08SPIV3)” for more information about using port E
pins as SPI pins.
Refer to Chapter 10, “Timer/PWM (S08TPMV2)” for more information about using port E pins as TPM
channel pins.
MC9S08AW60 Data Sheet, Rev 2
84
Freescale Semiconductor