MC9S08AW16CFUE Datasheet, PDF (31/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 2 Pins and Connections
Table 2-1. Pin Sharing Priority
Lowest <- Pin Function Priority -> Highest
Port Pins
Alternate Function Alternate Function
Reference¹
PTF3–PTF0
TPM1CH5–
TPM1CH2
Chapter 10, “Timer/PWM (S08TPMV2)”
PTG4–PTG0 KBI1P4–KBI1P0
Chapter 9, “Keyboard Interrupt (S08KBIV1)”
PTG6–PTG5 EXTAL–XTAL
Chapter 8, “Internal Clock Generator (S08ICGV4)”
1 _{See the listed chapter for information about modules that share these pins.}
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See the Chapter 6, “Parallel Input/Output” chapter for more details.
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTD7, PTD3,
PTD2, and PTG4 pins are controlled by the KBI module and are configured for rising-edge/high-level
sensitivity, the pullup enable control bits enable pulldown devices rather than pullup devices.
NOTE
When an alternative function is first enabled it is possible to get a spurious
edge to the module, user software should clear out any associated flags
before interrupts are enabled. Table 2-1 illustrates the priority if multiple
modules are enabled. The highest priority module will have control over the
pin. Selecting a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority module. It is
recommended that all modules that share a pin be disabled before enabling
another module.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
31