MC9S08AW16CFUE Datasheet, PDF (143/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 8 Internal Clock Generator (S08ICGV4)
8.4.4 FLL Engaged Internal Unlocked
FEI unlocked is a temporary state that is entered when FEI is entered and the count error (Δn) output from
the subtractor is greater than the maximum n_unlock or less than the minimum n_unlock, as required by the
lock detector to detect the unlock condition.
The ICG will remain in this state while the count error (Δn) is greater than the maximum n_lock or less than
the minimum n_lock, as required by the lock detector to detect the lock condition.
In this state the output clock signal ICGOUT frequency is given by f_ICGDCLK / R.
8.4.5 FLL Engaged Internal Locked
FLL engaged internal locked is entered from FEI unlocked when the count error (Δn), which comes from
the subtractor, is less than n_lock (max) and greater than n_lock (min) for a given number of samples, as
required by the lock detector to detect the lock condition. The output clock signal ICGOUT frequency is
given by f_ICGDCLK / R. In FEI locked, the filter value is updated only once every four comparison cycles.
The update made is an average of the error measurements taken in the four previous comparisons.
8.4.6 FLL Bypassed, External Clock (FBE) Mode
FLL bypassed external (FBE) is entered when any of the following conditions occur:
• From SCM when CLKS = 10 and ERCS is high
• When CLKS = 10, ERCS = 1 upon entering off mode, and off is then exited
• From FLL engaged external mode if a loss of DCO clock occurs and the external reference remains
valid (both LOCS = 1 and ERCS = 1)
In this state, the DCO and IRG are off and the reference clock is derived from the external reference clock,
ICGERCLK. The output clock signal ICGOUT frequency is given by f_ICGERCLK / R. If an external clock
source is used (REFS = 0), then the input frequency on the EXTAL pin can be anywhere in the range
0 MHz to 40 MHz. If a crystal or resonator is used (REFS = 1), then frequency range is either low for
RANGE = 0 or high for RANGE = 1.
8.4.7 FLL Engaged, External Clock (FEE) Mode
The FLL engaged external (FEE) mode is entered when any of the following conditions occur:
• CLKS = 11 and ERCS and DCOS are both high.
• The DCO stabilizes (DCOS = 1) while in SCM upon exiting the off state with CLKS = 11.
In FEE mode, the reference clock is derived from the external reference clock ICGERCLK, and the FLL
loop will attempt to lock the ICGDCLK frequency to the desired value, as selected by the MFD bits. To
run in FEE mode, there must be a working 32 kHz–100 kHz or 2 MHz–10 MHz external clock source. The
maximum external clock frequency is limited to 10 MHz in FEE mode to prevent over-clocking the DCO.
The minimum multiplier for the FLL, from Table 8-12 is 4. Because 4 X 10 MHz is 40MHz, which is the
operational limit of the DCO, the reference clock cannot be any faster than 10 MHz.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
143