MC9S08AW16CFUE Datasheet, PDF (139/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

8.3.4 ICG Status Register 2 (ICGS2)
Chapter 8 Internal Clock Generator (S08ICGV4)
R
W
Reset
Field
0
DCOS
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DCOS
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-9. ICG Status Register 2 (ICGS2)
Table 8-4. ICGS2 Register Field Descriptions
Description
DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error
has not changed by more than n_unlock for two consecutive samples and the DCO clock is not static. This bit is
used when exiting off state if CLKS = X1 to determine when to switch to the requested clock mode. It is also used
in self-clocked mode to determine when to start monitoring the DCO clock. This bit is cleared upon entering the
off state.
0 DCO clock is unstable.
1 DCO clock is stable.
8.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL)
R
W
Reset
Field
3:0
FLT
7
6
5
4
3
2
1
0
0
0
0
0
FLT
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-10. ICG Upper Filter Register (ICGFLTU)
Table 8-5. ICGFLTU Register Field Descriptions
Description
Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
139