MC9S08AW16CFUE Datasheet, PDF (88/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 6 Parallel Input/Output
6.6 Pin Behavior in Stop Modes
Depending on the stop mode, I/O functions differently as the result of executing a STOP instruction. An
explanation of I/O behavior for the various stop modes follows:
• Stop2 mode is a partial power-down mode, whereby I/O latches are maintained in their state as
before the STOP instruction was executed. CPU register status and the state of I/O registers should
be saved in RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon
recovery from stop2 mode, before accessing any I/O, the user should examine the state of the PPDF
bit in the SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had
occurred. If the PPDF bit is 1, I/O data previously stored in RAM, before the STOP instruction was
executed, peripherals may require being initialized and restored to their pre-stop condition. The
user must then write a 1 to the PPDACK bit in the SPMSC2 register. Access to I/O is now permitted
again in the user’s application program.
• In stop3 mode, all I/O is maintained because internal logic circuity stays powered up. Upon
recovery, normal I/O function is available to the user.
6.7 Parallel I/O and Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports and pin control
functions. These parallel I/O registers are located in page zero of the memory map and the pin control
registers are located in the high page register section of memory.
Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O and pin
control registers. This section refers to registers and control bits only by their names. A Freescale-provided
equate or header file normally is used to translate these names into the appropriate absolute addresses.
6.7.1 Port A I/O Registers (PTAD and PTADD)
Port A parallel I/O function is controlled by the registers listed below.
R
W
Reset
7
PTAD7
0
6
PTAD6
5
PTAD5
4
PTAD4
3
PTAD3
2
PTAD2
0
0
0
0
0
Figure 6-9. Port A Data Register (PTAD)
1
PTAD1
0
0
PTAD0
0
Table 6-2. PTAD Register Field Descriptions
Field
Description
7:0
PTAD[7:0]
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
MC9S08AW60 Data Sheet, Rev 2
88
Freescale Semiconductor