MC9S08AW16CFUE Datasheet, PDF (90/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 6 Parallel Input/Output
R
W
Reset
7
PTASE7
0
6
PTASE6
5
PTASE5
4
PTASE4
3
PTASE3
2
PTASE2
1
PTASE1
0
0
0
0
0
0
Figure 6-12. Output Slew Rate Control Enable for Port A (PTASE)
0
PTASE0
0
Table 6-5. PTASE Register Field Descriptions
Field
Description
7:0
PTASE[7:0]
Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
R
W
Reset
7
PTADS7
0
6
PTADS6
5
PTADS5
4
PTADS4
3
PTADS3
2
PTADS2
1
PTADS1
0
0
0
0
0
0
Figure 6-13. Output Drive Strength Selection for Port A (PTASE)
0
PTADS0
0
Table 6-6. PTASE Register Field Descriptions
Field
Description
7:0
PTADS[7:0]
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin.
0 Low output drive enabled for port A bit n.
1 High output drive enabled for port A bit n.
MC9S08AW60 Data Sheet, Rev 2
90
Freescale Semiconductor