MC9S08AW16CFUE Datasheet, PDF (89/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 6 Parallel Input/Output
R
W
Reset
7
PTADD7
0
6
PTADD6
5
PTADD5
4
PTADD4
3
PTADD3
2
PTADD2
1
PTADD1
0
0
0
0
0
0
Figure 6-10. Data Direction for Port A Register (PTADD)
0
PTADD0
0
Table 6-3. PTADD Register Field Descriptions
Field
Description
7:0
PTADD[7:0]
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
6.7.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS)
In addition to the I/O control, port A pins are controlled by the registers listed below.
R
W
Reset
7
PTAPE7
0
6
PTAPE6
5
PTAPE5
4
PTAPE4
3
PTAPE3
2
PTAPE2
0
0
0
0
0
Figure 6-11. Internal Pullup Enable for Port A (PTAPE)
1
PTAPE1
0
0
PTAPE0
0
Table 6-4. PTADD Register Field Descriptions
Field
Description
[7:0]
PTAPE[7:0]
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
89