MC9S08AW16CFUE Datasheet, PDF (303/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Appendix A Electrical Characteristics and Timing Specifications
A.11 SPI Characteristics
Table A-15 and Figure A-16 through Figure A-19 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
Num¹ C
Characteristic²
Symbol
Min
Max
Unit
Operating frequency³
Master f_op
f_Bus/2048
f_Bus/2
Hz
Slave _fop
dc
f_Bus/4
1
Cycle time
Master t_SCK
2
Slave _tSCK
4
2048
t_cyc
—
t_cyc
2
Enable lead time
Master _tLead
—
Slave _tLead
1/2
1/2
t_SCK
—
t_SCK
3
Enable lag time
Master _tLag
—
Slave _tLag
1/2
1/2
t_SCK
—
t_SCK
4
Clock (SPSCK) high time
Master and Slave
t_SCKH 1/2 t_SCK – 25
—
ns
5
Clock (SPSCK) low time Master
and Slave
t_SCKL ^{1/2 t}SCK ^{– 25}
—
ns
6
Data setup time (inputs)
Master _tSI(M)
30
Slave _tSI(S)
30
—
ns
—
ns
7
Data hold time (inputs)
Master _tHI(M)
30
Slave _tHI(S)
30
—
ns
—
ns
8
Access time, slave⁴
t_A
0
40
ns
9
Disable time, slave⁵
t_dis
—
40
ns
10
Data setup time (outputs)
Master _tSO
25
Slave _tSO
25
—
ns
—
ns
11
Data hold time (outputs)
Master _tHO
–10
Slave _tHO
–10
—
ns
—
ns
1 _{Refer to Figure A-16 through Figure A-19.}
2 _{All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI}
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
3 _{Maximum baud rate must be limited to 5 MHz due to pad input characteristics.}
4 _{Time to data active from high-impedance state.}
5 _{Hold time to high-impedance state.}
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
303