MC9S08AW16CFUE Datasheet, PDF (276/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 15 Development Support
15.4.1.1 BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
7
6
5
4
3
2
R
BDMACT
WS
ENBDM
BKPTEN
FTS
CLKSW
W
1
WSF
0
DVF
Normal
0
0
0
0
0
0
0
0
Reset
Reset in
1
1
0
0
1
0
0
0
Active BDM:
= Unimplemented or Reserved
Figure 15-5. BDC Status and Control Register (BDCSCR)
Table 15-2. BDCSCR Register Field Descriptions
Field
7
ENBDM
6
BDMACT
5
BKPTEN
4
FTS
3
CLKSW
Description
Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal
reset clears it.
0 BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow active background mode commands
Background Mode Active Status — This is a read-only status bit.
0 BDM not active (user application program running)
1 BDM active and waiting for serial commands
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored.
0 BDC breakpoint disabled
1 BDC breakpoint enabled
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode.
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
instruction
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
opcode)
Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC
clock source.
0 Alternate BDC clock source
1 MCU bus clock
MC9S08AW60 Data Sheet, Rev 2
276
Freescale Semiconductor