MC9S08AW16CFUE Datasheet, PDF (133/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 8 Internal Clock Generator (S08ICGV4)
8.1.3 Block Diagram
Figure 8-3 is a top-level diagram that shows the functional organization of the internal clock generation
(ICG) module. This section includes a general description and a feature list.
EXTAL
XTAL
V_DDA
(SEE NOTE 2)
V _SSA
(SEE NOTE 2)
ICG
OSCILLATOR (OSC)
WITH EXTERNAL REF
SELECT
ICGERCLK
FREQUENCY _DCO
LOCKED
REF
LOOP (FLL)
SELECT
CLOCK
SELECT
OUTPUT
ICGDCLK CLOCK
SELECT
IRG
INTERNAL ^{TYP 243 kHz}
REFERENCE _{8 MHz}
GENERATORS _RG
LOSS OF LOCK
AND CLOCK DETECTOR
ICGIRCLK
FIXED
CLOCK
SELECT
LOCAL CLOCK FOR OPTIONAL USE WITH BDC
/R
ICGOUT
FFE
ICGLCLK
NOTES:
1. See Table 8-9 for specific use of ICGOUT, FFE, ICGLCLK, ICGERCLK
2. Not all HCS08 microcontrollers have unique supply pins for the ICG. See the device pin assignments.
Figure 8-3. ICG Block Diagram
8.2 External Signal Description
The oscillator pins are used to provide an external clock source for the MCU. The oscillator pins are gain
controlled in low-power mode (default). Oscillator amplitudes in low-power mode are limited to
approximately 1 V, peak-to-peak.
8.2.1 EXTAL — External Reference Clock / Oscillator Input
If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as either
the external clock input or the input of the oscillator circuit as determined by REFS. If upon the first write
to ICGC1, either the FEI mode or SCM mode is selected, this pin is not used by the ICG.
8.2.2 XTAL — Oscillator Output
If upon the first write to ICGC1, either the FEE mode or FBE mode is selected, this pin functions as the
output of the oscillator circuit. If upon the first write to ICGC1, either the FEI mode or SCM mode is
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
133