MC9S08AW16CFUE Datasheet, PDF (222/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 13 Inter-Integrated Circuit (S08IICV1)
13.3.3 IIC Control Register (IIC1C)
7
6
5
4
3
2
1
0
R
0
0
0
IICEN
IICIE
MST
TX
TXAK
W
RSTA
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-5. IIC Control Register (IIC1C)
Table 13-4. IIC1C Register Field Descriptions
Field
7
IICEN
6
IICIE
5
MST
4
TX
3
TXAK
2
RSTA
Description
IIC Enable — The IICEN bit determines whether the IIC module is enabled.
0 IIC is not enabled.
1 IIC is enabled.
IIC Interrupt Enable — The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled.
1 IIC interrupt request enabled.
Master Mode Select — The MST bit is changed from a 0 to a 1 when a START signal is generated on the bus
and master mode is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode
of operation changes from master to slave.
0 Slave Mode.
1 Master Mode.
Transmit Mode Select — The TX bit selects the direction of master and slave transfers. In master mode this bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high.
When addressed as a slave this bit should be set by software according to the SRW bit in the status register.
0 Receive.
1 Transmit.
Transmit Acknowledge Enable — This bit specifies the value driven onto the SDA during data acknowledge
cycles for both master and slave receivers.
0 An acknowledge signal will be sent out to the bus after receiving one data byte.
1 No acknowledge signal response is sent.
Repeat START — Writing a one to this bit will generate a repeated START condition provided it is the current
master. This bit will always be read as a low. Attempting a repeat at the wrong time will result in loss of arbitration.
MC9S08AW60 Data Sheet, Rev 2
222
Freescale Semiconductor