MC9S08AW16CFUE Datasheet, PDF (76/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 5 Resets, Interrupts, and System Configuration
7
6
5
4
3
2
1
0
R
COPE
W
COPT
STOPE
0
0
Reset
1
1
0
1
0
0
1
1
= Unimplemented or Reserved
Figure 5-5. System Options Register (SOPT)
Table 5-5. SOPT Register Field Descriptions
Field
7
COPE
6
COPT
5
STOPE
Description
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
COP Watchdog Timeout — This write-once bit defaults to 1 after reset.
0 Short timeout period selected (2¹³ cycles of BUSCLK).
1 Long timeout period selected (2¹⁸ cycles of BUSCLK).
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
5.9.5 System MCLK Control Register (SMCLK)
This register is used to control the MCLK clock output.
7
6
5
4
3
2
1
0
R
0
0
0
0
MPE
W
MCSEL
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-6. System MCLK Control Register (SMCLK)
Table 5-6. SMCLK Register Field Descriptions
Field
4
MPE
2:0
MCSEL
Description
MCLK Pin Enable — This bit is used to enable the MCLK function.
0 MCLK output disabled.
1 MCLK output enabled on PTC2 pin.
MCLK Divide Select — These bits are used to select the divide ratio for the MCLK output according to the
formula below when the MCSEL bits are not equal to all zeroes. In the case that the MCSEL bits are all zero and
MPE is set, the pin is driven low. See Equation 5-1.
MCLK frequency = Bus Clock frequency ÷ (2 * MCSEL)
Eqn. 5-1
MC9S08AW60 Data Sheet, Rev 2
76
Freescale Semiconductor