MC9S08AW16CFUE Datasheet, PDF (101/324 Pages) Freescale Semiconductor, Inc – MC9S08AW60 Features

Chapter 6 Parallel Input/Output
6.7.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS)
In addition to the I/O control, port E pins are controlled by the registers listed below.
R
W
Reset
7
PTEPE7
0
6
PTEPE6
5
PTEPE5
4
PTEPE4
3
PTEPE3
2
PTEPE2
0
0
0
0
0
Figure 6-31. Internal Pullup Enable for Port E (PTEPE)
1
PTEPE1
0
0
PTEPE0
0
Table 6-24. PTEPE Register Field Descriptions
Field
Description
7:0
PTEPE[7:0]
Internal Pullup Enable for Port E Bits— Each of these control bits determines if the internal pullup device is
enabled for the associated PTE pin. For port E pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port E bit n.
1 Internal pullup device enabled for port E bit n.
R
W
Reset
7
PTESE7
0
6
PTESE6
5
PTESE5
4
PTESE4
3
PTESE3
2
PTESE2
1
PTESE1
0
0
0
0
0
0
Figure 6-32. Output Slew Rate Control Enable for Port E (PTESE)
0
PTESE0
0
Table 6-25. PTESE Register Field Descriptions
Field
Description
7:0
PTESE[7:0]
Output Slew Rate Control Enable for Port E Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.
MC9S08AW60 Data Sheet, Rev 2
Freescale Semiconductor
101