MC68HC908GT16_07 Datasheet, PDF (97/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Addr.
$0038
$0039
$003A
Input/Output (I/O) Registers
Register Name
ICG Trim Register ^Read:
(ICGTR) Write:
See page 100. _Reset:
Bit 7
TRIM7
1
6
TRIM6
0
5
TRIM5
0
4
TRIM4
0
3
TRIM3
0
2
TRIM2
0
1
TRIM1
0
Bit 0
TRIM0
0
ICG Divider Control ^Read:
DDIV3 DDIV2 DDIV1 DDIV0
Register (ICGDVR) Write:
See page 100. _{Reset: 0}
0
0
0
U
U
U
U
ICG DCO Stage Control ^Read:
Register (ICGDSR) Write:
See page 100. _Reset:
DSTG7
R
DSTG6
R
DSTG5
R
DSTG4 DSTG3
R
R
Unaffected by reset
DSTG2
R
DSTG1
R
DSTG0
R
= Unimplemented
R = Reserved
U = Unaffected
Figure 7-11. ICG Module I/O Register Summary (Continued)
Table 7-4. ICG Module Register Bit Interaction Summary
Register Bit Results for Given Condition
Condition
Reset
0
0
0
0
1
0
0
0 $15 $80 — —
OSCENINSTOP = 0,
STOP = 1
0
0
0
——
0
—
0
—
—
——
EXTCLKEN = 0
0
0
0
0
1
—
0
0
—
— uw uw
CMF = 1
— (1)
1
—
1
—
1
—
uw
uw uw uw
CMON = 0
0
0 (0) — — — — —
—
—
——
CMON = 1
— — (1) —
1
—
1
—
uw
uw uw uw
CS = 0
— — — (0)
1
———
—
— uw uw
CS = 1
— — — (1) — —
1
—
—
—
——
ICGON = 0
0
0
0
1 (0) 0
1
—
—
—
——
ICGON = 1
— — — — (1) — — —
—
— uw uw
ICGS = 0
us — us uc — (0) — —
—
—
—
—
ECGON = 0
0
0
0
0
1 — (0) 0
—
— uw uw
ECGS = 0
us — us us — — — (0) —
—
——
IOFF = 1
—
1* (1)
1
(1)
0
(1) —
uw
uw uw uw
EOFF = 1
— 1* (1) 0 (1) — (1) 0
uw
uw uw uw
N = written
(0) (0) (0) — — 0* — —
—
—
—
—
TRIM = written
(0) (0) (0) — — 0* — —
—
—
——
—
Register bit is unaffected by the given condition.
0, 1
Register bit is forced clear or set (respectively) in the given condition.
0*, 1*
Register bit is temporarily forced clear or set (respectively) in the given condition.
(0), (1) Register bit must be clear or set (respectively) for the given condition to occur.
us, uc, uw Register bit cannot be set, cleared, or written (respectively) in the given condition.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
97