MC68HC908GT16_07 Datasheet, PDF (133/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port D
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used
by the SPI module. However, the DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See Table 12-5.
SS — Slave Select
The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the
SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI
is enabled, the DDRB0 bit in data direction register B (DDRB) has no effect on the PTD0/SS pin.
12.5.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a
1 to a DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
6
5
4
3
2
1
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
0
0
0
0
0
0
0
Figure 12-14. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD7–DDRD0 — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears DDRD7–DDRD0, configuring all port D
pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 12-15 shows the port D I/O logic.
READ DDRD ($0007)
WRITE DDRD ($0007)
RESET
WRITE PTD ($0003)
DDRDx
PTDx
V_DD
PTDPUEx
30 k
PTDx
READ PTD ($0003)
Figure 12-15. Port D I/O Circuit
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
133