MC68HC908GT16_07 Datasheet, PDF (181/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

SIM Bus Clock Control and Generation
Addr.
$FE03
$FE04
$FE05
$FE06
Register Name
SIM Break Flag Control ^Read:
Register (SBFCR) Write:
See page 195. _Reset:
Interrupt Status ^Read:
Register 1 (INT1) Write:
See page 189. _Reset:
Interrupt Status ^Read:
Register 2 (INT2) Write:
See page 190. _Reset:
Interrupt Status ^Read:
Register 3 (INT3) Write:
See page 190. _Reset:
Bit 7
BCFE
0
IF6
R
0
IF14
R
0
0
R
0
6
5
R
R
IF5
IF4
R
R
0
0
IF13
IF12
R
R
0
0
0
0
R
R
0
0
= Unimplemented
4
3
2
R
R
R
IF3
IF2
IF1
R
R
R
0
0
0
IF11
IF10
IF9
R
R
R
0
0
0
0
0
0
R
R
R
0
0
0
R = Reserved
Figure 15-2. SIM I/O Register Summary (Continued)
1
Bit 0
R
R
0
0
R
R
0
0
IF8
IF7
R
R
0
0
IF16
IF15
R
R
0
0
15.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 15-3. This clock
originates from either an external oscillator or from the internal clock generator.
ECLK
ICLK
ICG
GENERATOR
CLOCK
SELECT
CIRCUIT
CS
COPCLK
TBMCLK
CGMXCLK
A
CGMOUT
÷2
B _S*
*WHEN S = 1,
CGMOUT = B
COP PRESCALER
TBM PRESCALER
SIM COUNTER
÷2
BUS CLOCK
GENERATORS
SIM
MONITOR MODE
USER MODE
ICG
Figure 15-3. System Clock Signals
15.2.1 Bus Timing
In user mode, the internal bus frequency is the internal clock generator output (CGMXCLK) divided by
four.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
181