MC68HC908GT16_07 Datasheet, PDF (55/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
ADCH4–ADCH0 — ADC Channel Select Bits
ADCH4–ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only eight
channels, AD7–AD0, are available on this MCU. The channels are detailed in Table 3-1. Care should
be taken when using a port pin as both an analog and digital input simultaneously to prevent switching
noise from corrupting the analog signal. See Table 3-1.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not being used.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
The voltage levels supplied from internal reference nodes, as specified in
Table 3-1, are used to verify the operation of the ADC converter both in production test and for user
applications.
Table 3-1. Mux Channel Select⁽¹⁾
ADCH4
0
0
0
0
0
0
0
0
0
↓
1
1
1
1
ADCH3
0
0
0
0
0
0
0
0
1
↓
1
1
1
1
ADCH2
0
0
0
0
1
1
1
1
0
↓
1
1
1
1
ADCH1
0
0
1
1
0
0
1
1
0
↓
0
0
1
1
ADCH0
0
1
0
1
0
1
0
1
0
↓
0
1
0
1
Input Select
PTB0/AD0
PTB1/AD1
PTB1/AD2
PTB2/AD3
PTB4/AD4
PTB5/AD5
PTB6/AD6
PTB7/AD7
Reserved
V_REFH
V_REFL
ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown or
reserved.
3.7.2 ADC Data Register
One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC
conversion completes.
Address: $003D
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-4. ADC Data Register (ADR)
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
55