MC68HC908GT16_07 Datasheet, PDF (60/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Configuration Register (CONFIG)
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. See Chapter 10 Low-Voltage Inhibit (LVI).
1 = LVI module power disabled
0 = LVI module power enabled
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. See Chapter 10 Low-Voltage Inhibit
(LVI) The voltage mode selected for the LVI should match the operating V_DD. See Chapter 20
Electrical Specifications for the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode.
0 = LVI operates in 3-V mode.
NOTE
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLCK cycles
NOTE
Exiting stop mode by an LVI reset will result in the long stop recovery.
The short stop recovery delay can be enabled when using the internal oscillator, a crystal, or a ceramic
resonator and the OSCENINSTOP bit is set. The short stop recovery delay can be enabled when an
external oscillator is used, regardless of the OSCENINSTOP setting.
The short stop recovery delay must be disabled (SSREC = 0) when the OSCENINSTOP bit is cleared.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 5 Computer Operating Properly (COP) Module.
1 = COP module disabled
0 = COP module enabled
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
60
Freescale Semiconductor