MC68HC908GT16_07 Datasheet, PDF (138/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Resets and Interrupts
RST PIN
CGMXCLK
INTERNAL
RESET
PULLED LOW BY MCU
32 CYCLES
32 CYCLES
Figure 13-1. Internal Reset Timing
13.2.3.1 Power-On Reset (POR)
A power-on reset (POR) is an internal reset caused by a positive transition on the V_DD pin. V_DD at the
POR must go completely to 0 V to reset the MCU. This distinguishes between a reset and a POR. The
POR is not a brown-out detector, low-voltage detector, or glitch detector.
A power-on reset:
• Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096
CGMXCLK cycles
• Drives the RST pin low during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay
• Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator
stabilization delay
• Sets the POR bit in the SIM reset status register and clears all other bits in the register
OSC1
PORRST⁽¹⁾
CGMXCLK
4096
32
32
CYCLES CYCLES CYCLES
CGMOUT
RST PIN
INTERNAL
RESET
1. PORRST is an internally generated power-on reset pulse.
Figure 13-2. Power-On Reset Recovery
13.2.3.2 Computer Operating Properly (COP) Reset
A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP
bit in the system integration module (SIM) reset status register.
To clear the COP counter and prevent a COP reset, write any value to the COP control register at location
$FFFF.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
138
Freescale Semiconductor