MC68HC908GT16_07 Datasheet, PDF (80/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Internal Clock Generator (ICG) Module)
7.3.1 Clock Enable Circuit
The clock enable circuit is used to enable the internal clock (ICLK) or external clock (ECLK) and the port
logic which is shared with the oscillator pins (OSC1 and OSC2). The clock enable circuit generates an
ICG stop (ICGSTOP) signal which stops all clocks (ICLK, ECLK, and the low-frequency base clock,
IBASE). ICGSTOP is set and the ICG is disabled in stop mode if the oscillator enable stop bit
(OSCENINSTOP) in the CONFIG2 register is clear. The ICG clocks will be enabled in stop mode if
OSCENINSTOP is high.
The internal clock enable signal (ICGEN) turns on the internal clock generator which generates ICLK.
ICGEN is set (active) whenever the ICGON bit is set and the ICGSTOP signal is clear. When ICGEN is
clear, ICLK and IBASE are both low.
The external clock enable signal (ECGEN) turns on the external clock generator which generates ECLK.
ECGEN is set (active) whenever the ECGON bit is set and the ICGSTOP signal is clear. ECGON cannot
be set unless the external clock enable (EXTCLKEN) bit in the CONFIG2 register is set. when ECGEN is
clear, ECLK is low.
The port E4 enable signal (PE4EN) turns on the port E4 logic. Since port E4 is on the same pin as OSC1,
this signal is only active (set) when the external clock function is not desired. Therefore, PE4EN is clear
when ECGON is set. PE4EN is not gated with ICGSTOP, which means that if the ECGON bit is set, the
port E4 logic will remain disabled in stop mode.
The port E3 enable signal (PE3EN) turns on the port E3 logic. Since port E3 is on the same pin as OSC2,
this signal is only active (set) when 2-pin oscillator function is not desired. Therefore, PE3EN is clear when
ECGON and the external crystal enable (EXTXTALEN) bit in the CONFIG2 register are both set. PE3EN
is not gated with ICGSTOP, which means that if ECGON and EXTXTALEN are set, the port E3 logic will
remain disabled in stop mode.
7.3.2 Internal Clock Generator
The internal clock generator, shown in Figure 7-3, creates a low frequency base clock (IBASE), which
operates at a nominal frequency (f_NOM) of 307.2 kHz ± 25 percent, and an internal clock (ICLK) which is
an integer multiple of IBASE. This multiple is the ICG multiplier factor (N), which is programmed in the
ICG multiplier register (ICGMR). The internal clock generator is turned off and the output clocks (IBASE
and ICLK) are held low when the internal clock generator enable signal (ICGEN) is clear.
The internal clock generator contains:
• A digitally controlled oscillator
• A modulo N divider
• A frequency comparator, which contains voltage and current references, a frequency to voltage
converter, and comparators
• A digital loop filter
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
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Freescale Semiconductor