MC68HC908GT16_07 Datasheet, PDF (246/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

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RST
0.1 μF
N.C. OSC2
1 μF
1 μF
DB9
2
3
1 _C1+
+
3 _C1–
4 _C2+
+
5 _C2–
7
8
MAX232
V_DD
9.8304 MHz CLOCK
OSC1
V_CC ¹⁶
0.1 μF
GND ¹⁵
V_TST
1 kΩ
V+ ²
V– ⁶
1 μF
10
9
+
1 μF
V_DD
9.1 V
+
10 kΩ
74HC125
6
5
74HC125
2
3
4
IRQ
PTA0
5
1
V_DDA
V_DD
V_DD
0.1 μF
V_DD
10 kΩ
PTC0
10 kΩ
PTC3
2 kΩ
PTC1
V_SS
V_SSA
Figure 19-12. Standard Monitor Mode
Table 19-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode
must be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one
of the following sets of conditions is met:
1. If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 4.9152 MHz with PTC3 low or 9.8304 MHz with PTC3 high
– IRQ = V_TST
2. If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = V_DD (this can be implemented through the internal IRQ pullup)
3. If $FFFE and $FFFF contain $FF (erased state):
– IRQ = V_SS (ICG is selected, no external clock required)
Once out of reset, the MCU waits for the host to send eight security bytes (see 19.3.2 Security). After the
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
NOTE
The PTA0 pin must remain high for 24 bus cycles after the RST pin goes
high to enter monitor mode properly.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
246
Freescale Semiconductor