MC68HC908GT16_07 Datasheet, PDF (247/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

Monitor Module (MON)
Table 19-1. Monitor Mode Signal Requirements and Options
Mode IRQ
RST
Reset
Vector
Serial
Comm.
Mode Selection
Divider
ICG
PTA0 PTC0 PTC1 PTC3
COP
Communication Speed
External Bus
Baud
Clock Frequency Range
Normal
V_TST V_DD or V_SS
X
1
1
0
0
OFF Disabled
4.9152
MHz
2.4576
MHz
9600
Monitor
V_TST V_DD or V_SS X
1
1
0
1
OFF Disabled
9.8304
MHz
2.4576
MHz
9600
V_DD
V_DD
$FFFF
(blank)
1
X
X
X
OFF Disabled
9.8304
MHz
2.4576
MHz
9600
Forced
Monitor
V_SS
V_DD
$FFFF
(blank)
1
X
X
X ON Disabled X
Nominal
2.4576
MHz
Nominal
9600
User
V_DD
or V_SS
V_DD
or V_SS
Not
$FFFF
X
X
X
X
X Enabled
X
X
X
MON08
Function
[Pin No.]
V_TST
[6]
RST
[4]
—
COM MOD0 MOD1 DIV4
[8]
[12] [14] [16]
—
—
OSC1
[13]
—
—
1. PTA0 must have a pullup resistor to VDD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600.
Baud rate using external oscillator is bus frequency / 256.
3. External clock is a 4.1952 MHz or 9.8304 MHz canned oscillator on OSC1.
4. X = don’t care.
5. MON08 pin refers to P&E Microcomputer Systems’ MONOUT-Cyclone 2 by 8-pin connector.
NC 1
NC 3
NC 5
NC 7
NC 9
NC 11
OSC1 13
V_DD 15
2 GND
4 RST
6 IRQ
8 PTA0
10 NC
12 PTC0
14 PTC1
16 PTC3
19.3.1.1 Normal Monitor Mode
When V_TST is applied to IRQ and PTC3 is low upon monitor mode entry, the bus frequency is a
divide-by-two of the input clock. If PTC3 is high with V_TST applied to IRQ upon monitor mode entry, the
bus frequency will be a divide-by-four of the input clock. Holding the PTC3 pin low when entering monitor
mode causes a bypass of a divide-by-two stage at the oscillator only if V_TST is applied to IRQ. In this
event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus
frequency.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
247