MC68HC908GT16_07 Datasheet, PDF (171/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
14.8.6 ESCI Data Register
The ESCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit
shift registers. Reset has no effect on data in the ESCI data register.
Address: $0018
Bit 7
6
Read: R7
R6
Write: T7
T6
Reset:
5
4
3
2
R5
R4
R3
R2
T5
T4
T3
T2
Unaffected by reset
1
Bit 0
R1
R0
T1
T0
Figure 14-16. ESCI Data Register (SCDR)
R7/T7:R0/T0 — Receive/Transmit Data Bits
Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018
writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register.
NOTE
Do not use read-modify-write instructions on the ESCI data register.
14.8.7 ESCI Baud Rate Register
The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for
both the receiver and the transmitter.
NOTE
There are two prescalers available to adjust the baud rate. One in the ESCI
baud rate register and one in the ESCI prescaler register.
Address:
Read:
Write:
Reset:
$0019
Bit 7
6
5
4
3
2
1
R
LINR
SCP1
SCP0
R
SCR2
SCR1
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 14-17. ESCI Baud Rate Register (SCBR)
Bit 0
SCR0
0
LINR — LIN Receiver Bits
This read/write bit selects the enhanced ESCI features for the local interconnect network (LIN) protocol
as shown in Table 14-6. Reset clears LINR.
Table 14-6. ESCI LIN Control Bits
LINR
0
1
1
M
Functionality
X Normal ESCI functionality
0 11-bit break detect enabled for LIN receiver
1 12-bit break detect enabled for LIN receiver
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
171