MC68HC908GT16_07 Datasheet, PDF(191/292 Page) Freescale Semiconductor, Inc – Microcontrollers

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MC68HC908GT16_07 Datasheet, PDF (191/292 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Low-Power Modes

Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This

protection allows registers to be freely read and written during break mode without losing status flag

information.

Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains

cleared even when break mode is exited. Status flags with a 2-step clearing mechanism â for example,

a read of one register followed by the read or write of another â are protected, even when the first step

is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step

will clear the flag as normal.

15.6 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby

situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is

described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition

code register, allowing interrupts to occur.

15.6.1 Wait Mode

In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 15-15 shows

the timing for wait mode entry.

IAB

WAIT ADDR

WAIT ADDR + 1

SAME

SAME

IDB

PREVIOUS DATA

NEXT OPCODE

SAME

SAME

R/W

Note: Previous data can be operand data or the WAIT opcode, depending on the

last instruction.

Figure 15-15. Wait Mode Entry Timing

A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled.

Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred.

In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the

module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.

Wait mode also can be exited by a reset or break. A break interrupt during wait mode sets the SIM break

stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the

CONFIG1 register is 0, then the computer operating properly module (COP) is enabled and remains

active in wait mode.

Figure 15-16 and Figure 15-17 show the timing for WAIT recovery.

MC68HC908GT16 â¢ MC68HC908GT8 â¢ MC68HC08GT16 Data Sheet, Rev. 5.0

Freescale Semiconductor

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